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My Account. Browse Catalog. Life Science Research Back. In still another embodiment, the methods 3 and 2 combined, the multi-layer structure by first forming a multi-layered structure of alternating n type over p type. Such a method is in the U. Patent 8,, and in “Silicon millefeuille: From a silicon wafer to multiple thin crystalline films in a single step” of Hernandez, et al. These methods take advantage of the fact that such n type silicon would become non-non-porous, while p type silicon would only require power for the anodization process to take place.

For these methods, the multilayer of n could be first etched over p to form the multilayer pattern, as in FIG 31E or 37E of U. Patent 8,, followed by an anodization process to convert the p-type silicon to porosity while leaving the n-type solid and unetched.

Then, the step of the oxidation step iii could be used to convert the porous layer into an insulating layer. The annealing step iv could be kept short or skipped because the n layers could be easily etched or not etched altogether. It was shown in [8] that the 3. Fathauer et al. November , dargestellt ist, was hierin durch Bezugnahme aufgenommen ist. Dem kann Oxidation, wie im Schritt iii.

Another alternative is an embodiment of the method 4 , according to which one forms multilayers of silicon over Si 1-x Ge x , as in “New class of Si-based superlattices: alternating layers of crystalline Si and porous amorphous Si 1-x Ge x alloys” of RW Fathauer et al.

In such a multilayer structure, there is a high degree of selectivity in the etching of Si 1-x Gex layers over Si layers. This may include oxidation as in step iii. Similar techniques could be used to form the basic structure for 3D memory. Zum Beispiel wurde so etwas wiedergegeben in Dokumenten von D. Kircher et al. There are known epitaxial processes in the art that allow good quality layers to be formed while keeping the process temperature low to avoid car doping.

For example, such has been reported in documents by D. These memory cells are controlled by memory control lines, such as bit lines, source lines, and word lines, usually in a rectangular array, so that by selecting a specific bit line and word line, one can select a specific memory cell to write to or read from there. In a 3D memory array having three dimensions, selecting a specific memory cell requires selection of a specific layer, which could be done by additional memory control lines, such as select lines.

As set forth herein, some of the select lines could be formed in the semiconductor layer within which the memory devices are formed e. Other selection lines could be deposited or formed by epitaxial growth.

These memory control lines could therefore include semiconductor materials such as silicon eg monocrystalline or conductive metal layers such as tungsten, aluminum or copper.

A preferred embodiment of monolithic 3D memory according to the present invention is demonstrated herein and outlined below. It employs monocrystalline transistors whose channels are vertically oriented so that the current flows vertically through the device across each of the device layers rather than horizontally along the device layers. The 3A illustrates the starting material structure for these vertically oriented 3D memories. The selection of the thickness of these layers could be based on the consideration of etch choice, auto-doping, dopant diffusion due to thermal budget, etch rate and short channel effect, memory interference and so on.

The thickness of each of these layers could be , , , nm, up to hundreds of nm. Suppression of dopant diffusion can be achieved through the use of low temperature epitaxial processes, for example the AMAT – deg C epi process. Interlayer diffusion barriers may also be employed, such as as thin as single, double, or multiple atomic layers of a diffusion suppressor, such as carbon. These inter-layer diffusion barriers can be integrated within the multi-layer epitaxial growth process.

Also, the doping of each layer may not be uniformly profiled but vertically profiled to enhance or suppress physical processes such as hot carrier injection according to the specific application requirements of the device. Patent 8,, specified in detail and described herein. Patent 8,, is taught, all of which is incorporated herein by reference. Entsprechend hat die Multischichtstruktur , die durch die Verfahren gebildet sind, die hierin dargestellt sind, Einkristallschichten, die eine Atomebenenausrichtung zwischen den Schichten haben, anders als bei einer Multischichtstruktur, die durch Techniken gebildet wurden, wie einen sukzessiven Schichttransfer.

An interesting aspect of the multilayer structure that is epitaxially based, rather than the film transfer approach, is that in most cases the entire structure would resemble a monolithic crystal in which the crystal repeating element could be a silicon atom or other molecules that align well over the layers , No molecular level alignment would occur in a layer transfer process.

Thus, in an epitaxial process of multilayering the molecules that make up the multilayer structure, all lines that are better than 0. Accordingly, the multi-layer structure has formed by the methods illustrated herein, single crystal layers having atomic plane alignment between the layers, unlike a multilayer structure formed by techniques such as a successive layer transfer.

Such a multilayer structure could be created on top of a cut layer, as in FIGS 1A to 2 to allow transfer of the complete multi-layer structure and, correspondingly, processing of both sides of the multi-layer structure. If a cut layer was used, then the multilayer structure of the end device could have a connection and circuits on its top and bottom surface without a thick amount of silicon greater than 40 microns.

The usage of Cut-layer or pattern transfer techniques presented herein and in the technology incorporated herein by reference could assist in forming thin-isolation support circuits and interconnects to the memory structure, such as , , , nm or 0.

One skilled in the art would be able to modify the flow for other alternative embodiments. The 3B illustrates the structure after ‘valleys’ etching, which is multi-layer burrs and valleys therebetween, resulting in a repetitive ridge structure leads.

The width of the ridges and valleys could be from 10 nm to a few hundred nm. For example, the valleys and ridges could have similar widths or other ratios, such as 50 nm valleys with a nm ridge, and can be constructed for the specific target structure.

Many of the drawings herein depict a section or section of a 3D structure with either 2D drawings of a sectional plane or 3D perspective drawings. Generally, the direction along the ridge is referred to as the ‘X’ direction, orthogonal to the ridge is referred to as the ‘Y’ direction , and is designated along the epitaxial layer growth – the vertical direction as the Z direction.

The 3C illustrates the high etch selectivity of SiGe versus silicon that can be performed in this example using the Applied Material Selectra Etching System. Alternatively, the selective etching may be performed using wet chemical etching. For example, with these 3D structures, the multilayer might be 3A with layers that could be selectively etched, such as silicon single crystal, or poly or amorphous , SiGe mixture of silicon and germanium , P doped silicon, N doped silicon, etc.

A selective plasma etching process can be used. Alternatively, a two-step process could be used by first forming pores in the desired regions of the channel layers by selective anodization processing, then using plasma etching of the porous regions. Alternativ kann die Ladungsfangschicht ein defektreiches hoch-k Dielektrikum oder siliziumreiches Siliziumnitrid sein. Alternativ kann die Ladungsfangschicht durch ein schwimmendes Gate ersetzt sein.

Dies kann durch thermische Oxidation, Atomschichtdeposition ALD oder alternative Prozesse erfolgen, die zur Halbleitervorrichtungsherstellung verwendet werden. Alternatively, the charge trapping layer may be a high-k dielectric rich in defects or silicon-rich silicon nitride. Alternatively, the charge trapping layer may be replaced by a floating gate. This can be done by thermal oxidation, atomic layer deposition ALD or alternative processes used for semiconductor device fabrication.

A slight retouch etch can also be used to remove any remaining stringer. The etching step could be done in two steps. Conductive etch stop layers can be used. The 3G FIG. The remaining soil material could serve as a common grounding strip. The lower gate line could serve as the ground select gate and the upper gate line string select gate can serve as the string selection.

The resulting structure forms a matrix of vertically oriented non-volatile NAND memory cells. The 3I illustrates the 3D NAND memory structure after adding the grid of memory control lines: word lines , Bit lines , String select lines and ground selection lines ,. Es beginnt von der Struktur , die in der 3B oben dargestellt ist. Zuerst durch Beschichten der Gratstruktur mit einer dielektrischen Multischicht einer Tunneloxidschicht, Ladungsfangschicht, wie Siliziumnitrid, und Blockieroxidschicht, was den Ladungsspeicherstapel bildet.

Ein Gate-Material , so wie stark dotiertes Polysilizium, Metall, wie Wolfram, oder anderes leitendes Material wird nachfolgend abgeschieden. It starts from the structure in the 3B is shown above. Marking and etching techniques are used in gate piles in the ‘y’ direction.

First by coating the ridge structure with a dielectric multilayer of a tunnel oxide layer, charge trapping layer, such as silicon nitride, and blocking oxide layer, forming the charge storage stack forms. A gate material , such as heavily doped polysilicon, metal, such as tungsten, or other conductive material is subsequently deposited. Then patterning by masking and etching techniques may be used to form elongate strips in ‘y’ direction perpendicular to the burr direction.

Alternatively, gate stacks may be formed by filling the pre-patterned space within the oxide, which is referred to as a damascene process. Alternatively, the gate stack may be formed by replacing the dummy gate, which is called the replacement gate process.

The deposition step could use ALD techniques. Alternatively, a combination of thermal oxide and other deposition techniques could be used. Die 4B illustriert einen Querschnitt der Struktur von 4A.

The memory could be set up as a matrix of memory blocks. Each memory block could be a right-angled X in the x direction and Y in the y direction, with each direction 1 – 2. And the number of layers could be , , , These are examples, and larger or smaller numbers could also be designed. Preferably, at the staircase structure region, the P layers may be etched and replaced by oxide or other insulating material.

Similarly, the P layers between two adjacent word lines may be etched and replaced by oxide or other insulating material not shown herein. Selective isotropic etching of the P type layers could be used to etch between the horizontal N type stripes.

Die Auswahlleitungen stellen pro Grat Steuerung bereit. The 4C Figure 3 illustrates the 3D NOR structure after forming a staircase to the per-layer interconnect on the marginal edge and adding control lines. The selector cables provide control per burr.

SL1 controls access to the first ridge, SL2 controls the second ridge, SL3 controls the third ridge and so on. On the other hand, the overhead area required for the stair interconnect structure will excite longer lines to secure the device value and reduce cost per bit. The burr selection control device may be removed by first removing the channel material at the region intended for burr selection control. The select gate transistors may be designed to function as branchless transistors ‘JLT’ , also known as the gate around nano-lines.

Such thinning would narrow these regions to about 20 nm thick, or about 15 nm, or about 10 nm. Patent 8,, all of the foregoing is incorporated herein by reference, including its teachings of memory control and the subsequent adaptation to control the 3D NOR structure herein. An additional enhancement to such a 3D NOR is to break the gate control into two independent side gates – even gates in the even valleys and odd gates in the odd valleys – to control a ridge, such as in the 5A is shown.

Such a division could allow a doubling of the storage capacity. To support reading or holding the memory states. These two gate control lines may be placed on the upper connection layer side as in FIG 5A is shown, or alternatively one on the top and one below the bottom, as in the 5B is shown. If these two gate control lines are both placed on the top side, the technology node for the top side connection may be more advanced than the technology node used for the 3D memory block.

Eine solche Technologie ist in dem US Patent 7,, detailliert, das hierin durch Bezugnahme aufgenommen ist. These two improvements could be combined to allow ‘4 bits per cell’, as in the 5C is shown. Such a technology is in the U. Patent 7,, in detail, which is incorporated herein by reference. Using this concept teaches a technology that works in the US Patent 6,, which is incorporated herein by reference as to how to add an additional center bit for 3 bits per facet and a total of 6 bits per channel.

Eine andere bekannte Verbesserung ist, die Ladungsmenge, die in einer gegebenen Ladungsfangstelle gespeichert wird, zu steuern, um Multilevel-Spannungen pro Zelle zu gestatten, Womit mehr als 1 Bit pro Speicherplatz kodiert wird. Another known improvement is to control the amount of charge stored in a given charge trapping site to allow for multilevel voltages per cell, which encodes more than 1 bit per memory location. These various enhancement techniques could be combined to achieve an even higher number of bits per cell.

Likewise, if each space is designed to hold 4 levels, then the cell could 8th Save bits and even 12 bits with the center place. If more levels are managed on each storage location, then the storage capacity could be even higher. An additional alternative to consider the high density, multi-bit per cell memory is a refreshable memory or volatile memory. Generally, this is the conventional requirement for the non-volatile memory devices 10 Years of data retention time.

Some of the techniques described herein for increases in storage capacity could be challenged by keeping those stored voltages for the full 10 years, especially with devices that could operate in high temperature environments, or with the motivation to scale down cell size or tunnel oxide.

An alternative solution is to periodically tune the device to the desired state in a fixed or variable time interval, such as days, weeks, months or a few years. Alternatively, a memory controller could read and verify the degree of charge loss or difference and make adjustments.

If the integrity of some memory locations has dropped below a set threshold, these memories could be refreshed to repair the memory locations to the full charge level. Such self-monitoring could be done with minimal impact on normal device operations or their overall energy consumption.

Als Ergebnis steht die Spannung, die an die linken Bitleitungen angelegt wird, nicht im Konflikt mit der Spannung, die an die rechten Bitleitungen angelegt wird. The 5E illustrates an alternative 3D NOR memory block without using burr select gates use with stairs on either side of the ridge – left staircase and right staircase. The particular channel selection could be done by appropriately allocating connections along ridges and along planes.

As an example, all even planes may be with select lines, such as SL1 with level 2 , SL2 with level 4 , SL3 with level 6 and so on, be connected. The selection lines can also be considered as source lines. This could be done for the left stairs and the right stairs. Then, along the ridge, for each ridge, the left staircase could be used around the left bitline 1 LBL1 with burr 1 , Levels 1 and 5 and 9 etc. As a result, the voltage applied to the left bit lines does not conflict with the voltage applied to the right bit lines.

In addition, two levels of bit cells in a ridge can be accessed simultaneously. In a single operation cycle, two levels of bit cells can be read through left and right bit lines. In a single operation cycle, one level of bit cells may be read from one side of the bit line, while the other level of bit cells may be described by the opposite side of the bit line. In a similar approach, any specific memory location could be selected by selecting a select line, a bitline, and a wordline.

Forming stairs on both edges of the ridge, for example, as in the 5E is advantageous, even if a pro ridge selection is used. For devices having multiple memory blocks, the value efficiency can be improved by dividing each staircase between both the right and left sides of adjacent blocks.

The number of layers that make up the 3D NOR structure could increase over time to respond to demands to increase device capacity. For a large number of layers, the vertical access time could become large enough to affect the effective access time between lower levels and upper levels. An optional solution to maintain the symmetry and equalization of access duration could be to use access from both sides of the device.